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this document is a general product description and is subject to change without notice. hynix do es not assume any responsibilit y for use of circuits described. no patent licenses are implied. rev 1.2 / jul. 2008 1 1gbit mobile ddr sdram ba sed on 16m x 4bank x16 i/o specification of 1gb (64mx16bit) mobile ddr sdram memory cell array - organized as 4banks of 16,777,216 x16
rev 1.2 / jul. 2008 2 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series document title 1gbit (4bank x 16m x 16 bit) mobile ddr sdram revision history revision no. history draft date remark 0.1 - initial draft sep. 2007 preliminary 0.2 - defined idd6 current spec. dec. 2007 preliminary 0.3 - insert idd8 spec. value (see page22) dec. 2007 preliminary 0.4 - modify : idd5 : 100ma --> 120ma idd6 (@45 o c , full bank) : 450ua --> 500ua jan. 2008 preliminary 1.0 - final version mar. 2008 1.1 - modify : idd6 (@45 o c , full bank) : 500ua --> 450ua idd6 (@85 o c , one bank) : 550ua --> 500ua may. 2008 1.2 - insert ddr400 dc/ac characteristics jul. 2008
rev 1.2 / jul. 2008 3 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series features summary ? mobile ddr sdram - double data rate architec ture: two data transfer per clock cycle ? mobile ddr sdram interface - x16 bus width - multiplexed address (row address and column ad- dress) ? supply voltage - 1.8v device: vdd and vddq = 1.7v to 1.95v ? memory cell array - 1gbit (x16 device) = 16m x 4bank x 16 i/o ? data strobe - x16 device: ldqs and udqs - bidirectional, data strobe (dqs) is transmitted and re- ceived with data, to be used in capturing data at the receiver - data and data mask referenced to both edges of dqs ? low power features - pasr (partial array self refresh) - auto tcsr (temperature compensated self refresh) - ds (drive strength) - dpd (deep power down): dpd is an optional feature, so please contact hynix office for the dpd feature ? input clock - differential clock inputs (ck, ck ) ? data mask - ldm and udm: input mask signals for write data - dm masks write data-in at the both rising and falling edges of the data strobe ? mode rerister set, extended mode regis- ter set and status register read - keep to the jedec standard regulation (low power ddr sdram) ? cas latency - programmable cas latency 2 or 3 supported ? burst length - programmable burst length 2 / 4 / 8 with both sequen- tial and interleave mode ? auto precharge - option for each burst access ? auto refresh and self refresh mode ? clock stop mode - clock stop mode is a feature supported by mobile ddr sdram. - keep to the jedec standard regulation ? initializing the mobile ddr sdram - occurring at device power up or interruption of device power ? package - 60 ball, lead free fbga
rev 1.2 / jul. 2008 4 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series description the hynix h5ms1g62mfp series is 1,073 ,741,824-bit cmos low power double da ta rate synchronous dram (mobile ddr sdram), ideally suited for mobile applications which us e the battery such as pdas, 2.5g and 3g cellular phones with internet access and multimedia ca pabilities, mini-notebook, hand-held pcs. it is organized as 4banks of 16,777,216 x16. the hynix h5ms1g62mfp series uses a double-data-rate arch itecture to achieve high-sp eed operation. the double data rate architecture is essentially a 2 n prefetch architecture with an interface designed to transfer two data per clock cycle at the i/o pins. the hynix h5ms1g62mfp series of fers fully synchronous operations referenced to both rising and falling edges of the clock. while all address and control in puts are latched on the rising edges of the ck (mobile ddr sdram operates from a differential clock : the crossing of ck going high and ck going low is referred to as the positive edge of ck ), data, data strobe and data mask inputs are samp led on both rising and falling edges of it ( input data is registered on both edges of dqs, and output data is referenced to both edges of dqs, as well as to both edges of ck ). the data paths are internally pipelined and 2-bit prefetched to achieve high bandwidth. all input voltage levels are compatible with lvcmos. read and write accesses to the low power ddr sdram (mob ile ddr sdram) are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then fo llowed by a read or write command. the address bits reg- istered coincident with the active command are used to sele ct the bank and the row to be accessed. the address bits registered coincident with the read or write command are used to select the bank and the starting column location for the burst access. the low power ddr sdram (mobile ddr sdram) provides for programmable read or write bursts of 2, 4 or 8 loca- tions. an auto precharge function may be enabled to provid e a self-timed row precharge that is initiated at the end of the burst access. as with standard sdram, the pipeline d and multibank architectu re of low power ddr sd ram (mobile ddr sdram) allows for concurrent operation, thereb y providing high effective bandwidth by hiding row precharge and activation times. the low power ddr sdram (mobile ddr sd ram) also provides for special prog rammable self refresh options which are partial array self refresh (full, half, quarter and 1/8 and 1/16 array) and temperature compensated self refresh. a burst of read or write cycles in progress can be interru pted and replaced by a new burst read or write command on any cycle (this pipelined design is not restricted by a 2n rule). only read bursts in progress with auto precharge disa- bled can be terminated by a burst terminate command. bu rst terminate command is undefined and should not be used for read with autoprecharge enabled and for write bursts.
rev 1.2 / jul. 2008 5 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series the hynix h5ms1g62mfp series has the special low power function of auto tcsr (temperature compensated self refresh) to reduce self refresh current consumption. since an internal temperature sensor is implemented, it enables to automatically adjust refresh rate according to temperature without external emrs command. deep power down mode is an addition al operating mode for low power ddr sdram (mobile ddr sdram). this mode can achieve maximum power reduction by removing power to the memory array within low power ddr sdram (mobile ddr sdram). by using this feature, the system can cut off almost all dram power without adding the cost of a power switch and giving up mother-board power-line layout flexibility. all inputs are lvcmos compatible. devices will have a v dd and v ddq supply of 1.8v (nominal). the hynix h5ms1g62mfp series is av ailable in the following package: - 60 ball fbga [ size : 8mm x 12mm, t=1.0mm max ] 1gb mobile ddr sdram ordering information part number clock frequency organization interface package h5ms1g62mfp-e3m 200mhz(cl3) / 83mhz(cl2) 4banks x 16mb x 16 lvcmos 60 ball fbga lead free h5ms1g62mfp-j3m 166mhz(cl3) / 83mhz(cl2) h5ms1g62mfp-k3m 133mhz(cl3) / 83mhz(cl2) H5MS1G62MFP-L3M 100mhz(cl3) / 66mhz(cl2)
rev 1.2 / jul. 2008 6 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series information for hyni x known good die with the advent of multi-chip package (mcp), package on package (pop) and system in a package (sip) applications, customer demand for known good die (kgd) has increased. requirements for smaller form factors and higher memory de nsities are fueling the need for wafer-level memory solu- tions due to their superior flexibility. hynix known good die (kgd) products ca n be used in packaging technologies such as systems-in-a-package (sip) an d multi-chip package (mcp) to reduce the board area required, making them ideal for hand-held pcs, and many ot her portable digital applications. hynix mobile sdram will be able to continue its constant effort of enabling the advanced package products of all appli- cation customers. - please contact hynix office for hynix kg d product availability and informations.
rev 1.2 / jul. 2008 7 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series 60ball fbga assignment vss vddq vssq vddq vssq vss cke a9 dq15 dq13 dq11 dq9 udqs udm ck a11 a b c d e f g h a6 a7 j vss a4 k vssq dq14 dq12 dq10 dq8 nc /ck a12 a8 a5 vddq dq1 dq3 dq5 dq7 a13 /we /cs a10 a2 dq0 dq2 dq4 dq6 ldqs ldm /cas ba0 a0 a3 vdd vssq vddq vssq vddq vdd /ras ba1 a1 vdd 123456789 top view
rev 1.2 / jul. 2008 8 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series mobile ddr sdram pin descriptions symbol type description ck, ck input clock: ck and ck are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck . output (read) data is referenced to th e crossings of ck and ck (both directions of crossing). cke input clock enable: cke high activates, and cke low deactivates internal clock signals, device input buffers and output drivers. taking cke low provides precharge power-down and self refresh operation (all banks idle), or active power-down (row active in any bank). cke is synchronous for all functions except for self refresh exit, which is achieved asynchronously. cs input chip select: cs enables (registered low) and disables (registered high) the command decoder. all commands are masked when cs is registered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. ras , cas , we input command inputs: ras , cas and we (along with cs ) define the command being entered ba0, ba1 input bank address inputs: ba0 and ba1 define to which bank an active, read, write or precharge command is being applied. ba0 an d ba1 also determine which mode register is to be loaded during a mode register set command (mrs, emrs or srr). a0 ~ a13 input address inputs: provide the row address for active commands, and the column address and auto precharge bit for read/write comma nds, to select one location out of the memory array in the respective bank. the address inputs also provide the op-code during a mode register set command. a10 sampled during a precharge command deter- mines whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by ba0, ba1. for 1gb (x16), row address: a0 ~ a13, column address: a0 ~ a9 auto-precharge flag: a10 dq0 ~ dq15 i/o data bus: data input / output pin ldm ~ udm input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled. high along with that input data during a write access. dm is sampled on both edges of dqs. data mask pins incl ude dummy loading internally, to match the dq and dqs loading. for x16 devices, ldm corresponds to the data on dq0-dq7, and udm corresponds to the data on dq8-dq15. ldqs ~ udqs i/o data strobe: output with read data, input wi th write data. edge-aligned with read data, center-aligned with write data. used to capture write data. for x16 device, ldqs correspond s to the data on dq0-dq7, and udqs corresponds to the data on dq8-dq15. v dd supply power supply v ss supply ground v ddq supply i/o power supply v ssq supply i/o ground nc - no connect: no internal el ectrical connection is present.
rev 1.2 / jul. 2008 9 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series functional block diagram 16mbit x 4banks x 16 i/o mobile ddr sdram 16 sense amp & i/o gate output buffer & logic address register mode register state machine address buffers bank select row active cas latency clk cke /cs /ras /cas /we ldm ~udm a0 a1 ba1 ba0 a13 pasr refresh dq0 dq15 row decoders row decoders row decoders row decoders column decoders 16mx16 bank0 16mx16 bank1 16mx16 bank2 16mx16 bank3 memory cell array data out control burst length /clk input buffer & logic ds 32 16 32 data strobe transmitter data strobe receiver ds ldqs ~ udqs extended mode register self refresh logic & timer internal row counter write data register 2-bit prefetch unit row pre decoder column pre decoder column add counter burst counter column active
rev 1.2 / jul. 2008 10 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series register definition i mode register set (mrs ) for mobile ddr sdram ba1 ba0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 000000 000 cas latency bt burst length burst type a3 burst type 0sequential 1interleave burst length a2 a1 a0 burst length a3 = 0 a3=1 0 0 0 reserved reserved 00 1 2 2 01 0 4 4 01 1 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 reserved reserved cas latency a6 a5 a4 cas latency 0 0 0 r e s e r v e d 0 0 1 r e s e r v e d 0 1 0 2 0 1 1 3 1 0 0 reserved 1 0 1 r e s e r v e d 1 1 0 r e s e r v e d 1 1 1 reserved
rev 1.2 / jul. 2008 11 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series register definition ii extended mode register set (emrs) for mobile ddr sdram ba1 ba0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 100000000 ds 00 pasr ds (drive strength) a6 a5 drive strength 00full 0 1 half (default) 10quarter 11octant pasr (partial array self refresh) a2 a1 a0 self refresh coverage 000all banks (default) 001half of total bank (ba1=0) 0 1 0 quarter of total bank (ba1=ba0=0) 0 1 1 reserved 1 0 0 reserved 101 one eighth of total bank (ba1 = ba0 = row address msb=0) 110 one sixteenth of total bank (ba1 = ba0 = row address 2 msbs=0) 1 1 1 reserved
rev 1.2 / jul. 2008 12 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series register definition iii status register (sr) for mobile ddr sdram note) 1. the revision number starts at ?0000? an d increments by ?0001? each time a change in the manufacturer?s specification, ibis, or process occurs. 2. low temperature out of range. 3. high temperature out of range - no refresh rate can guar antee func tionality. 4. the refresh rate multiplier is base d on the memory?s temperature sensor. 5. required average periodic refr esh interval = trefi * multiplier. 6. status register is only for read. 7. to read out status register values, ba [1:0] set to 01b and a[13:0] set to all 0 wi th mrs command followed by read command with that ba[1:0] and a[13:0] are don?t care. ba1 ba0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0100000000000000 dq15 dq14 dq13 dq12 dq11 dq10 dq9 dq8 dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 density - dw refresh rate revision identi fication manufacturers identification 01100xxxx 1) x 1) x 1) x 1) 0110 density dq15 dq14 dq13 density 000 128 001 256 010 512 0 1 1 1024 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved dw (device width) dq11 device width 0 16 bits 1 32 bits refresh rate dq10 dq9 dq8 refresh rate 00x 4 2) 010 4 011 2 100 1 101 0.5 110 0.25 111 0.25 3) manufacturers identification dq3 dq2 dq1 dq0 manufacturer 0110 hynix xxxx reserved or other companies
rev 1.2 / jul. 2008 13 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series command truth table dm truth table note: 1. all states and se quences not shown are illegal or reserved. 2. deslect and nop are func tionally interchangeable. 3. autoprecharge is non-persistent. a10 high enables autoprecharge, while a10 lo w disables autoprecharge 4. burst terminate applies to only read bursts with auto precharge disabled. this command is undefined and should not be used f or read with autoprecharge enab led, and for write bursts. 5. this command is burst terminate if cke is high and deep power down entry if cke is low. 6. if a10 is low, bank address determines which bank is to be precharged. if a10 is high, all banks are precharged and ba0-ba1 are don ' t care. 7. this command is auto refresh if cke is high, and self refresh if cke is low. 8. all address inputs and i/o are '' don ' t care '' except for cke. internal refresh coun ters control bank and row addressing. 9. all banks must be precharged before issu ing an auto-refresh or self refresh command. 10. ba0 and ba1 value select among mrs, emrs and srr. 11. used to mask write data, provided coincident with the corresponding data. 12. cke is high for all commands shown except self refresh and deep power-down. function cs ras cas we ba a10/ap addr note deselect (nop) h x x x x x x 2 no operation (nop) l h h h x x x 2 active (select bank and activate row) l l h h v row row read (select bank and column and start read burst) l h l h v l col read with ap (read burst with autoprecharge) l h l h v h col 3 write (select bank and column and start write burst) lh l lv l col write with ap (write burst with autoprecharge) l h l l v h col 3 burst terminate or enter deep power down l h h l x x x 4, 5 precharge (deactivate row in selected bank) l l h l v l x 6 precharge all (deactivate rows in all banks) l l h l x h x 6 auto refresh or enter self refresh l l l h x x x 7,8,9 mode register set l l l l v op code 10 function dm dq note write enable l valid 11 write inhibit h x 11
rev 1.2 / jul. 2008 14 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series cke truth table note: 1. cken is the logic stat e of cke at clock edge n ; cke n -1 was the state of cke at the previous clock edge. 2. current state is the state of lp ddr immediately prior to clock edge n . 3. command n is the command registered at clock edge n, and action n is the result of command n . 4. all states and se quences not shown are illegal or reserved. 5. deselect and nop are fu nctionally interchangeable. 6. power down exit time (t xp ) should elapse before a command othe r than nop or deselect is issued. 7. self refresh exit time (t xsr ) should elapse before a command othe r than nop or deselect is issued. 8. the deep power-down exit procedure must be followed as discussed in the deep power-down section of the functional descriptio n. 9. the clock must toggle at least one time during the t xp period. 10. the clock must toggle at least once during the t xsr time. cke n-1 cke n current state command n action n note l l power down x maintain power down l l self refresh x maintain self refresh l l deep power down x maintain deep power down l h power down nop or deselect exit power down 5,6,9 l h self refresh nop or deselect exit self refresh 5,7,10 l h deep power down nop or deselect exit deep power down 5,8 h l all banks idle nop or deselect precharge power down entry 5 hlbank(s) activenop or deselect active power down entry 5 h l all banks idle auto re fresh self refresh entry h l all banks idle burst terminate enter deep power down h h see the other truth tables
rev 1.2 / jul. 2008 15 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series current state bank n truth table (command to bank n ) note: 1. the table applies when both cke n -1 and cke n are high, and after t xsr or t xp has been met if the previous state was self refresh or power down. 2. deselect and nop are fu nctionally interchangeable. 3. all states and sequences not shown are illegal or reserved. 4. this command may or may not be bank specific. if all banks ar e being precharged, they must be in a valid state for prechargi ng. 5. a command other than nop should not be issued to the same ba nk while a read or write burst wi th auto precharge is enabled. 6. the new read or write command could be auto precharge enabled or auto precharge disabled. current state command action notes cs ras cas we description any h x x x deselect (nop) continue previous operation l h h h nop continue previous operation idle l l h h active select and activate row l l l h auto refresh auto refresh 10 l l l l mode register set mode register set 10 l l h h precharge no action if bank is idle row active l h l h read select column & start read burst l h l l write select column & start write burst l l h l precharge deactivate row in bank (or banks) 4 read (without auto recharge) lh l h read truncate read & start new read burst 5,6 lh l l write truncate read & start new write burst 5,6,13 l l h l precharge truncate read, start precharge l h h l burst terminate burst terminate 11 write (without auto precharge) lh l h read truncate write & start new read burst 5,6,12 lh l l write truncate write & start new write burst 5,6 l l h l precharge truncate write, start precharge 12
rev 1.2 / jul. 2008 16 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series 7. current state definitions: idle: the bank has been precharged, and trp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precha rge disabled, and has not yet te rminated or been terminated. write: a write burst has been initiated, with auto prec harge disabled, and has not yet te rminated or been terminated. 8. the following states must not be interrupt ed by a command issued to the same bank. deselect or nop commands or allowable commands to the other bank should be issued on any clock edge occurring during these states. allowable co mmands to the other bank are determined by its current state and truth table3, and accordin g to truth table 4. precharging: starts with the registra tion of a precharge co mmand and ends when t rp is met. once t rp is met, the bank will be in the idle state. row activating: starts with registrati on of an active command and ends when t rcd is met. once t rcd is met, the bank will be in the '' row active '' state. read with ap enabled: starts with the registration of the read command with auto precharge enabled and ends when t rp has been met. once t rp has been met, the bank will be in the idle state. write with ap enabled: starts with registration of a write command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank will be in the idle state. 9. the following states must not be in terrupted by any executable command; deselect or nop commands must be applied to each positive clock edge during these states. refreshing: starts with registration of an auto refresh co mmand and ends when t rfc is met. once t rfc is met, the lp ddr will be in an '' all banks idle '' state. accessing mode register: starts with registration of a mode register set command and ends when tmrd has been met. once t mrd is met, the lp ddr will be in an '' all banks idle '' state. precharging all: starts with the registra tion of a precharge all command and ends when t rp is met. once t rp is met, the bank will be in the idle state. 10. not bank-specific; requires that all banks are idle and no bursts are in progress. 11. not bank-specific. burst terminate affects the most recent read burst, regardless of bank. 12. requires appropriate dm masking. 13. a write command may be applied after the completion of the re ad burst; otherwise, a burst te rminate must be used to end the read prior to asserting a write command.
rev 1.2 / jul. 2008 17 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series current state bank n truth table (command to bank m ) current state command action notes cs ras cas we description any h x x x deselect (nop) continue previous operation l h h h nop continue previous operation idle x x x x any any command allowed to bank m row activating, active, or pre- charging l l h h active activate row l h l h read start read burst 8 l h l l write start write burst 8 l l h l precharge precharge read with auto precharge dis- abled l l h h active activate row l h l h read start read burst 8 l h l l write start write burst 8,10 l l h l precharge precharge write with auto precharge dis- abled l l h h active activate row l h l h read start read burst 8,9 l h l l write start write burst 8 l l h l precharge precharge read with auto precharge l l h h active activate row l h l h read start read burst 5,8 l h l l write start write burst 5,8,10 l l h l precharge precharge write with auto precharge l l h h active activate row l h l h read start read burst 5,8 l h l l write start write burst 5,8 l l h l precharge precharge
rev 1.2 / jul. 2008 18 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series note: 1. the table applies when both cke n -1 and cke n are high, and after t xsr or t xp has been met if the previous state was self refresh or power down. 2. deselect and nop are fu nctionally interchangeable. 3. all states and sequences not shown are illegal or reserved. 4. current state definitions: idle: the bank has been precharged, and trp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with au to precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminate d. 5. read with ap enabled and write with ap enabled: the read with autopr echarge enabled or write with autoprecharge enabled states can be broken into two parts: the access period and the precharge period. for read with ap, the precharge period is defined as if the same burs t was executed with auto precharge disabled and then followed with t he earliest possible precharge command that still ac cesses all the data in the burst. for write with auto precharge, t he precharge period begins when t wr ends, with t wr measured as if auto precharge was disabled. the access period starts with registration of the command and ends where th e precharge period (or t rp ) begins. during the precharge period, of the read with autoprecharge enabled or wr ite with autoprecharge enabled stat es, active, precharge, read, and write commands to the other bank may be applie d; during the access period, only active and precharge commands to the other banks may be applied. in either case, all other related limitations apply (e.g. contention between rea d data and write data must be avoided). 6. auto refresh, self refresh, and mode register set commands may only be issued when all bank are idle. 7. a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 8. reads or writes listed in the command column incl ude reads and writes with auto precharge enabled and reads and writes with auto precharge disabled. 9. requires appropriate dm masking. 10. a write command may be applied after the completion of data output, otherwise a burst terminate command must be issued to end the read prior to asserting a write command.
rev 1.2 / jul. 2008 19 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series absolute maximum rating ac and dc operating conditions operating condition clock inputs (ck, ck ) address and command inputs (a0~an, ba0, ba1, cke, cs , ras , cas , we ) data inputs (dq, dm, dqs) data outputs (dq, dqs) parameter symbol rating unit operating case temperature t c -30 ~ 85 o c storage temperature t stg -55 ~ 150 o c voltage on any pin relative to v ss v in , v out -0.3 ~ v ddq +0.3 v voltage on v dd relative to v ss v dd -0.3 ~ 2.7 v voltage on v ddq relative to v ss v ddq -0.3 ~ 2.7 v short circuit output current i os 50 ma power dissipation p d 0.7 w parameter symbol min typ max unit note supply voltage v dd 1.7 1.8 1.95 v 1 i/o supply voltage v ddq 1.7 1.8 1.95 v 1 operating case temperature t c -25 85 o c parameter symbol min max unit note dc input voltage v in -0.3 v ddq+ 0.3 v dc input differential voltage v id(dc) 0.4*v ddq v ddq+ 0.6 v 2 ac input differential voltage v id(ac) 0.6*v ddq v ddq+ 0.6 v 2 ac differential crosspoint voltage v ix 0.4*v ddq 0.6*v ddq v3 parameter symbol min max unit note input high voltage v ih 0.8*v ddq v ddq+ 0.3 v input low voltage v il -0.3 0.2*v ddq v parameter symbol min max unit note dc input high voltage v ihd(dc) 0.7*v ddq v ddq+ 0.3 v dc input low voltage v ild(dc) -0.3 0.3*v ddq v ac input high voltage v ihd(ac) 0.8*v ddq v ddq+ 0.3 v ac input low voltage v ild(ac) -0.3 0.2*v ddq v parameter symbol min max unit note dc output high voltage (ioh = -0.1ma) v oh 0.9*v ddq -v dc output low voltage (iol = 0.1ma) v ol -0.1*v ddq v
rev 1.2 / jul. 2008 20 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series leakage current note: 1. all voltages are referenced to vss = 0v and vssq must be same potential and vddq must not exceed the level of vdd. 2. vid(dc) and vid(ac) are the magnitude of the difference between the input level on ck and the input level on ck . 3. the value of vix is expected to be 0.5*vddq and must track variations in the dc level of the same. 4. v in = 0 to 1.8v. all other pins are not tested under v in =0v. 5. d out is disabled. v out = 0 to 1.95v. ac operating test condition note: 1. the circuit shown on th e right represents the timing load used in defining the relevant timing parameters of the part. it is not intended to be either a precise repre- sentation of the typical system environment nor a depic- tion of the actual load pres ented by a production tester. system designers will use ibis or other simulation tools to correlate the timing refere nce load to system environ- ment. manufacturers will correlate to their production (generally a coaxial transmission line terminated at the tester electronics). for the ha lf strength driver with a nominal 10pf load parameters tac and tqh are expected to be in the same range. however, these parameters are not subject to production test but are estimated by design and characterization. use of ibis or other simulation tools for system design validation is suggested. input / output capacitance note: 1. these values are guarante ed by design and are tested on a sample base only. 2. these capacitance values are for single monolithic devices only. multiple die packages will have parallel capacitive loads. 3. input capacitance is measured according to jep147 procedure for measuring capacitance using a vector network analyzer. vdd, vddq are applied and all other pins (except the pi n under test) floating. dq ' s should be in high impedance state. this may be achieved by pulling cke to low level. 4. although dm is an input-only pin, the input capacitance of this pin must model the input capacitance of the dq and dqs pins. this is required to match signal propagation times of dq, dqs and dm in the system. parameter symbol min max unit note input leakage current i li -1 1 ua 4 output leakage current i lo -1.5 1.5 ua 5 parameter symbol value unit note ac input high/low level voltage v ih / v il 0.8*v ddq /0.2*v ddq v input timing measurement reference level voltage v trip 0.5*v ddq v input rise/fall time t r / t f 1ns output timing measurement reference level voltage v outref 0.5*v ddq v output load capacitance for access time measurement cl pf 1 parameter symbol speed unit note min max input capacitance, ck, ck cck 1.5 3.5 pf input capacitance delta, ck, ck cdck - 0.25 pf input capacitance, all other input-only pins ci 1.5 3.0 pf input capacitance delta, all other input-only pins cdi - 0.5 pf input/output capacitance, dq, dm, dqs cio 2.0 4.5 pf 4 input/output capacitance delta, dq, dm, dqs cdio - 0.5 pf 4 test load for full drive strength buffer (20 pf) test load for half drive strength buffer (10 pf) 0vuqvu z o =50 ?
rev 1.2 / jul. 2008 21 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series mobile ddr output slew rate characterristics note: 1. measured with a test load of 20pf connected to vssq 2. output slew rate for rising edge is measured between vild(dc) to vihd(ac) and for falling edge between vihd(dc) to vild(ac) 3. the ratio of pull-up slew rate to pull -down slew rate is specified for the same te mperature and voltage, over the entire tem perature and voltage range. for a given output, it represents the ma ximum difference between pull-up an d pull-down drivers due to proces s variation. mobile ddr ac overshoot / undershoot specification note: 1. this specification is intended for devices with no clamp protection and is guaranteed by design. parameter min max unit note pull-up and pull-down slew rate for full strength driver 0.7 2.5 v/ns 1, 2 pull-up and pull-down slew rate for half strength driver 0.3 1.0 v/ns 1, 2 output slew rate matching rati o (pull-up to pull-down) 0.7 1.4 - 3 parameter specification maximum peak amplitude allowed for overshoot 0.5v maximum peak amplitude allowed for undershoot 0.5v the area between overshoot signal and vd d must be less than or equal to 3v-ns the area between undershoot signal and gnd must be less than or equal to 3v-ns 2.5v 2.0v 1.5v 1.0v 0.5v 0.0v -0.5v overshoot undershoot vdd vss max. amplitude = 0.5v max. area = 3v-ns time (ns) voltage (v)
rev 1.2 / jul. 2008 22 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series dc characteristics parameter symbol test condition max unit note ddr 400 ddr 333 ddr 266 ddr 200 operating one bank active-precharge current idd0 trc = trc(min); tck = tck(min); cke is high; cs is high between valid commands; address inputs are switching; data bus inputs are stable 80 60 50 40 ma 1 precharge power-down standby current idd2p all banks idle; cke is low; cs is high; tck = tck(min); address and control inputs are switching; data bus inputs are stable 0.4 ma precharge power-down standby current with clock stop idd2ps all banks idle; cke is low; cs is high; ck = low; ck = high; address and control inputs are switching; data bus inputs are stable 0.4 ma precharge non power-down standby current idd2n all banks idle; cke is high; cs is high, tck = tck(min); address and control inputs are switching; data bus inputs are stable 10 ma precharge non power-down standby current with clock stop idd2ns all banks idle; cke is high; cs is high; ck = low; ck = high; address and control inputs are switching; data bus inputs are stable 15 5 active power-down standby current idd3p one bank active; cke is low; cs is high; tck = tck(min); address and control inputs are switching; data bus inputs are stable 83 ma active power-down standby current with clock stop idd3ps one bank active; cke is low; cs is high; ck = low; ck = high; address and control inputs are switching; data bus inputs are stable 2 active non power-down standby current idd3n one bank active; cke is high; cs is high; tck = tck (min); address and control inputs are switching; data bus inputs are stable 15 12 ma active non power-down standby current with clock stop idd3ns one bank active; cke is high; cs is high; ck = low; ck = high; address and control inputs are switching; data bus inputs are stable 86ma operating burst read cur- rent idd4r one bank active; bl=4; cl=3; tck = tck (min) ; continuous read bursts; iout=0ma; address in- puts are switching, 50% data change each burst transfer 150 90 80 70 ma 1 operating burst write cur- rent idd4w one bank active; bl=4; tck=tck (min) ; continu- ous write bursts; address inputs are switching; 50% data change each burst transfer 140 90 80 65 ma auto refresh current idd5 trc=trfc (min) ; tck=tck (min); burst refresh; cke is high; address and control inputs are switching; data bus inputs are stable 120 ma self refresh current idd6 cke is low; ck=low; ck =high; extended mode register set to all 0's; address and control inputs are st able; data bus inputs are stable see next page ua 2 deep power down current idd8 address, control and data bus inputs are stable 10 ua 4
rev 1.2 / jul. 2008 23 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series note: 1. idd specifications are tested afte r the device is properly initialized 2. input slew rate is 1v/ns 3. definitions for idd: low is defined as v in 0.1 * v ddq high is defined as v in 0.9 * v ddq stable is defined as inputs stable at a high or low level switching is defined as - address and command: inputs changing between high and low once per two clock cycles - data bus inputs: dq changing between high and low once per clock cycle dm and dqs are stable 4. please contact hynix office for more in formation and ability for dpd operation. deep power down operation is a hynix optiona l function. 5. all idd values are guarante ed by full range of operat ing voltage and temperature. vdd, vddq = 1.7v ~ 1.95v. temperature = -30 o c ~ +85 o c dc characteristics - i dd6 note: 1. related numerical values in this 45 o c are examples for reference sample value only. 2. with a on-chip temperature sensor, auto temperature compensate d self refresh will automatically adjust the interval of self- refresh operation according to case temperature variations. t e m p . ( o c) memory array unit 4 banks 2 banks 1 bank 45 450 350 300 ua 85 900 650 500 ua
rev 1.2 / jul. 2008 24 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series ac characteristics (ac operating conditions unless ot herwise noted) (sheet 1 of 2) parameter symbol ddr400 ddr333 ddr266 ddr200 unit note min max min max min max min max dq output access time (from ck, ck ) t ac 2.0 5.0 2.0 5.0 2.5 6.0 2.5 7.0 ns dqs output access time (from ck, ck ) t dqsck 2.0 5.0 2.0 5.0 2.5 6.0 2.5 7.0 ns clock high-level width t ch 0.45 0.55 0.45 0.55 0. 45 0.55 0.45 0.55 tck clock low-level width t cl 0.45 0.55 0.45 0.55 0. 45 0.55 0.45 0.55 tck clock half period t hp tcl, tch (min) - tcl, tch (min) - tcl, tch (min) - tcl, tch (min) - ns 1,2 system clock cycle time cl = 3 t ck3 5 - 6.0 - 7.5 - 10 - ns 3 cl = 2 t ck2 12 12 12 - 15 - ns dq and dm input setup time t ds 0.54 0.6 0.8 1.1 ns 4,5,6 dq and dm input hold time t dh 0.54 0.6 0.8 1.1 ns 4,5,6 dq and dm input pulse width t dipw 1.6 - 1.6 - 1.6 - 2.2 - ns 7 address and control input setup time t is 0.9 1.1 1.3 1.5 ns 6,8,9 address and control input hold time t ih 0.9 1.1 1.3 1.5 ns 6,8,9 address and control input pulse width t ipw 2.2 - 2.2 - 2.6 - 3.0 - ns 7 dq & dqs low-impedance time from ck, ck t lz 1.0 - 1.0 - 1.0 - 1.0 - ns 10 dq & dqs high-impedance time from ck, ck t hz 5.0 5.0 6.0 7.0 ns 10 dqs - dq skew t dqsq 0.4 0.5 0.6 0.7 ns 11 dq / dqs output hold time from dqs t qh thp - tqhs thp - tqhs thp - tqhs thp - tqhs ns 2 data hold skew factor t qhs 0.5 0.65 0.75 1.0 ns 2 write command to 1st dqs latching transi- tion t dqss 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tck dqs input high-level width t dqsh 0.4 0.4 0.4 0.4 tck dqs input low-level width t dqsl 0.4 0.4 0.4 0.4 tck dqs falling edge of ck setup time t dss 0.2 0.2 0.2 0.2 tck dqs falling edge hold time from ck t dsh 0.2 0.2 0.2 0.2 tck
rev 1.2 / jul. 2008 25 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series ac characteristics (ac operating conditions unless ot herwise noted) (sheet 2 of 2) parameter symbol ddr400 ddr333 ddr266 ddr200 unit note min max min max min max min max mode register set command period t mrd 2-2-2-2-tck mrs(srr) to read command period t srr 2-2-2-2-tck minimum time between status register read to next valid command t src cl+1 - cl+1 - cl+1 - cl+1 - tck write preamble setup time t wpres 0-0-0-0-ns12 write postamble t wpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck 13 write preamble t wpre 0.25 - 0.25 - 0.25 - 0.25 - tck read preamble cl = 3 t rpre 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tck 14 cl = 2 t rpre 0.5 1.1 0.5 1.1 0.5 1.1 0.5 1.1 tck 14 read postamble t rpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck active to precharge command period t ras 40 70,00 0 42 70,00 0 45 70,00 0 50 70,00 0 ns active to active command period t rc 55 - 60 - 75 - 80 - ns auto refresh to active/auto refresh command period t rfc 110 - 110 - 110 - 110 - ns active to read or write delay t rcd 15 - 18 - 22.5 - 30 - ns 15 precharge command period t rp 15 - 18 - 22.5 - 30 - ns 15 active bank a to active bank b delay t rrd 10 - 12 - 15 - 15 - ns write recovery time t wr 15 - 15 - 15 - 15 - ns auto precharge write recovery + precharge time t dal (twr/tck) + (trp/tck) tck 16 internal write to read command delay t wtr 2-1-1-1-tck self refresh exit to next valid command de- lay t xsr 140 - 140 - 140 - 140 - ns exit power down to next valid command de- lay t xp tis + 2clk - tis + 1clk - tis + 1clk - tis + 1clk -ns cke min . pulse width (high and low) t cke 1-1-1-1-tck average periodic refresh interval t refi -7.8-7.8-7.8-7.8us17 refresh period t ref -64-64-64-64ms
rev 1.2 / jul. 2008 26 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series note: 1. min (t cl , t ch ) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specific ation limits for t cl and t ch ) 2. t qh = t hp - t qhs , where thp = minimum half clock period for any given cycle and is defined by clock high or clock low (t cl , t ch ). t qhs accounts for 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of dqs on one transition followed by the worst case pull-in of dq on the next transition, both of which are, separately, due to data pin skew and output pattern effects , and p-channel to n-channel variation of the output drivers. 3. the only time that the clock frequenc y is allowed to change is during clock stop, power-down or self-refresh modes. 4. the transition time for dq, dm and dqs inputs is measured between v il (dc) to v ih (ac) for rising input signals, and v ih (dc) to v il (ac) for falling input signals. 5. dqs, dm and dq input slew rate is specified to prevent double clocking of data and preserve setup and hold times. signal tra nsitions through the dc region must be monotonic. 6. input slew rate 1.0 v/ns. 7. these parameters guarantee device timing but they are not necessarily tested on each device. 8. the transition time for address and command inputs is measured between v ih and v il . 9. a ck/ck differential slew rate of 2.0 v/ ns is assumed for this parameter. 10. t hz and t lz transitions occur in the same access time windows as vali d data transitions. these parameters are not referred to a specific voltage level, but specify when the device is no longer driving (hz), or begins driving (lz). 11. t dqsq consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle. 12. the specific requirement is that dqs be valid (high, low, or some point on a valid transition) on or before this ck edge. a valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previously in progress on the bus, dqs will be transitioning from hi-z to lo gic low. if a previous write was in progress, dqs could be high, low, or transitioning from high to low at this time, depending on t dqss . 13. the maximum limit for this parameter is not a device limit. the device operates wi th a greater value for this parameter, bu t system performance (bus turnaround ) will degrade accordingly. 14. a low level on dqs may be maintained during high-z states (d qs drivers disabled) by adding a weak pull-down element in the system. it is recommended to turn off the weak pull-down el ement during read and write bu rsts (dqs drivers enabled). 15. speed bin (cl-t rcd -t rp ) = 3-3-3 16. minimum 3clk of tdal(= twr+trp) is required because it n eed minimum 2clk for twr and minimum 1clk for trp. t dal = (t wr /t ck ) + (t rp /t ck ): for each of the terms above, if not already an integer, round to the next higher integer. 17. a maximum of eight refresh commands can be posted to any given low power dd r sdram (mobile ddr sd ram), meaning that the maximum absolute interval between any refresh command and the next refresh command is 8*t refi . 18. all ac parameters are guaranteed by full range of operating voltage and temperature. vdd, vddq = 1.7v ~ 1.95v. temperature = -30 o c ~ +85 o c.
rev 1.2 / jul. 2008 27 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series mobile ddr sdram operation state diagram idle all bank pcg. auto refresh self refresh pcg. power down (e)mrs set write read precharge all active power down row active mrs, emrs refs ckel refa ckeh act ckel ckeh write write read refsx command input automatic sequence deep power down power on pcg. all banks power applied dpds dpdsx burst stop writea read reada bst read a write a writea reada read pre pre pre srr read srr read reada act : active bst : burst ckel : enter power-down ckeh : exit power-down dpds : enter deep power-down dpdsx : exit deep power- downemrs emrs : ext. mode reg. set mrs : mode register set pre : precharge preall : precharge all banks refa : auto refresh refs : enter self refresh refsx : exit self refresh read : read w/o auto precharge reada : read with auto precharge write : write w/o auto precharge writea : write with auto precharge srr : status register read
rev 1.2 / jul. 2008 28 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series deselect the deselect function (cs = high) prevents new commands from being executed by the mobile ddr sdram. the mobile ddr sdram is effectively deselected. oper ations already in progress are not affected. no operation the no operation (nop) command is used to perform a nop to a mobile ddr sdram that is selected (cs = low). this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. (see to next figure) active the active command is used to activate a row in a particular bank for a subsequent read or write access. the value of the ba0,ba1 inputs selects the bank, and the address provided on a0-a13 (or the highest address bit) selects the row. (see to next figure) before any read or write commands can be issued to a bank within the mobile ddr sdram, a row in that bank must be opened. this is accomplished via the active comm and, which selects both the ba nk and the row to be acti- vated. the row remains active until a precharge (or read with auto precharge or write with auto precharge) com- mand is issued to the bank. a precharge (or read with auto precharge or write wi th auto precharge) command must be issued before opening a different row in the same bank. cs a0~a13 we cas don't care clk clk cke ba0, ba1 bank address row address don't care ra ba nop command active command ras cs a0~a13 we cas clk clk cke ba0, ba1 ras (high) (high)
rev 1.2 / jul. 2008 29 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series once a row is open (with an active command) a read or wr ite command may be issued to that row, subject to the t rcd specification. t rcd ( min ) should be divided by the clock period an d rounded up to the next whole number to determine the earliest clock edge after the active comma nd on which a read or write command can be entered. a subsequent active command to a different row in the same bank can only be issued after the previous active row has been closed (precharge). the minimum time interval between successi ve active commands to the same bank is defined by t rc . a subsequent active command to another bank can be issued while the first bank is bein g accessed, which results in a reduction of total row-access overhead. the minimum time interval between successive active commands to differ- ent banks is defined by t rrd. don't care once a row is open(with an active command) a read or write command may be issued to that row , subject to the trcd specification. trcd (min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the active command on which a read or write command can be entered. /clk clk nop nop nop nop trcd command address write a with a/p bank b act nop bank a act bank a col bank b row bank a row bank a act bank a row trrd trc
rev 1.2 / jul. 2008 30 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series read / write command the read command is used to initiate a burst read to an active row. the value of ba0 and ba1 selects the bank and address inputs select the starting column location. the value of a10 determines whether or not auto precharg e is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent access. the valid data-out elements will be available cas latency after the read command is issued. the mobile ddr drives the dqs during read operations. the in itial low state of the dqs is known as the read preamble and the last data-out element is coinci dent with the read postamble. dqs is edge-aligned with read data. upon com- pletion of a burst, assuming no new read command s have been initiated, the i/o's will go high-z. the write command is used to initiate a burst write access to an active row. the value of ba0, ba1 selects the bank and address inputs select the starting column location. the value of a10 determines whether or not auto precharg e is used.if auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent access. input data appearing on the data bus, is written to the memory ar ray subject to the dm input logic level appearing coincident with the data. if a given dm signal is registered low, the corresponding data will be written to the memory; if the dm signal is registered high , the corresponding data-inputs will be ignored, and a write will not be executed to that byte/col umn location. the memory controller drives the dqs during write operations. the initial low state of the dqs is known as the write preamble and the low state foll owing the last data-in element is write postamble. upon completion of a burst, assuming no new commands have been initiated, the i/o's will stay high-z and any additional input data will be ignored. read / write command don't care ca ba high to enable auto precharge low to disable auto precharge read command write command ca ba clk clk cke clk clk cke (high) (high) cs a0~a9 we cas a10 ras ba0, ba1 cs a0~a9 we cas a10 ras ba0, ba1
rev 1.2 / jul. 2008 31 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series read the basic read timing parameters for dq are shown next fi gure (basic read timing para meters). they apply to all read operations. during read bursts, dqs is driven by the mobile ddr sdram along with the output data. the initial low state of the dqs is known as the read preamble; the low state coincident with last data-out element is known as the read postamble. basic read timing parameters do n do n+1 do n+2 do n+3 /clk clk tck tck tch tcl trpre tdqsck tdqsq max tac tlz tqh tdqsck tqh tqh thz tqh trpre tdqsck tlz tdqsck trpst tac tdqsq max do n do n+1 do n+2 do n+3 dqs dq dqs dq don't care 1) do n : data out from column n 2) all dq are vaild tac after the ck edge all dq are vaild tdqsq after the dqs edge, regardless of tac trpst tacmax tacmin tqh thz
rev 1.2 / jul. 2008 32 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series the first data-out element is edge aligned with the first ri sing edge of dqs and the successive data-out elements are edge aligned to successive edges of dqs. this is shown in next figure with a cas latency of 2 and 3. upon completion of a read burst, assuming no other read command has been initiated, the dq will go to high-z. read burst showing cas latency /clk clk do n do n read nop nop nop nop nop ba, col n cl =3 cl =2 don't care 1) do n : data out from column n 2) ba, col n = bank a, column n 3) burst length = 4; 3 subseqnent elements of data out appear in the programmed order following do n 4) shown with nominal tac, tdqsck and tdqsq command address dqs dq dqs dq
rev 1.2 / jul. 2008 33 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series read to read data from a read burst may be concat enated or truncated by a subsequent read command. the first data from the new burst follows either the last elemen t of a completed burst or the last desi red element of a longer burst that is being truncated. the new read command should be issued x cycles after the first read command, where x equals the number of desired data-out element pairs (pairs are required by the 2n prefetch architecture). consecutive read bursts a read command can be initiated on any clock cycle follow ing a previous read command. non-consecutive reads are shown in the first figure of next page. random read acce sses within a page or pages can be performed as shown in second figure of next page. /clk clk do n do n read nop read nop nop nop ba, col n cl =3 cl =2 don't care 1) do n (or b ): data out from column n (or column b) 2) ba, col n (b) = bank a, column n (b) 3) burst length = 4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first) 4) read bursts are to an active row in any bank 5) shown with nominal tac, tdqsck and tdqsq command address dqs dq dqs dq ba, col b do b do b
rev 1.2 / jul. 2008 34 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series non-consecutive read bursts random read bursts /clk clk do n do n read nop nop read nop nop ba, col n cl =3 cl =2 don't care 1) do n (or b ): data out from colum n n (or colum n b) 2) ba, col n (b) = bank a, colum n n (b) 3) burst length = 4; 3 subsequent elem ents of d ata o ut appear in the program m ed order follow ing d o n (b) 4) show n w ith nom inal tac, td q sck and td q sq command address dqs dq dqs dq ba, col b do b /clk clk do n do x' do n read read read read nop nop ba, col n cl =3 cl =2 don't care 1) do n, etc: d ata out from colum n n, etc n ', x', etc : d ata o u t elem ents, accoding to the program m d burst order 2) ba, col n = bank a, column n 3) burst length = 2, 4 or 8 in cases show n (if burst of 4 or 8, the burst is interrupted) 4) read are to active rows in any banks command address dqs dq dqs dq ba, col b do b ba, col x ba, col g do n' do x do x' do b' do g do g' do n' do x do b do b'
rev 1.2 / jul. 2008 35 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series read burst terminate data from any read burst may be truncated with a bu rst terminate command. the burst terminate latency is equal to the read (cas) latency, i.e. , the burst terminate command should be issued x cycles after the read com- mand where x equals the desired data-out element pairs. terminating a read burst /clk clk read burst terminate nop nop nop nop ba, col n cl =3 cl =2 don't care 1) do n : data out from column n 2) ba, col n = bank a, column n 3) cases shown are bursts of 4 or 8 terminated after 2 data elements 4) shown with nominal tac, tdqsck and tdqsq command address dqs dq dqs dq
rev 1.2 / jul. 2008 36 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series read to write data from read burst must be completed or truncated before a subsequent write command can be issued. if trun- cation is necessary, the burst terminate command must be used, as shown in next fig. for the case of nominal t dqss . read to write /clk clk do n do n read bst nop write nop ba, col n cl =3 cl =2 don't care 1) do n = data out from column n; di b = data in to column b 2) burst length = 4 or 8 in the cases shown; if the burst length is 2, the bst command can be ommitted 3) shown with nominal tac, tdqsck and tdqsq command address dqs dq dqs dq ba, col b nop dm read bst nop nop nop ba, col n command address ba, col b write tdqss di b di b
rev 1.2 / jul. 2008 37 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series read to precharge a read burst may be followed by or truncated with a precharge command to the same bank (provided auto pre- charge was not activated). the precharge command should be issued x cycles after the read command, where x equal the number of desired data-out element pairs. following the precharge command, a subsequent command to the same bank cannot be issued until trp is met. note that part of the row precharge time is hidden during the access of the last data-o ut elements.in the case of a read being executed to completion, a precharge command issued at the optimum time (as described above) pro- vides the same operation that would result from read burst with auto precharge enabled. the disadvantage of the precharge command is that it requ ires that the command and ad dress buses be available at the appropriate time to issue the command. the advantage of the precharge command is that it can be used to truncate bursts. read to precharge /clk clk do n do n read nop pre nop nop act ba, col n cl =3 cl =2 don't care 1) do n = data out from column n 2) cases shown are either uninterrupted burst of 4, or interrupted bursts of 8 3) shown with nominal tac, tdqsck and tdqsq 4) precharge may be applied at (bl / 2) tck after the read command. 5) note that precharge may not be issued before tras ns after the active command for applicable banks. 6) the active command may be applied if trc has been met. command address dqs dq dqs dq bank ( a or all) ba, row trp
rev 1.2 / jul. 2008 38 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series write input data appearing on the da ta bus, is written to the memory array su bject to the dm input logic level appearing coincident with the data. if a given dm signal is registered low, the correspond ing data will be written to the memory; if the dm signal is registered high, the corresponding data inputs will be ignored, and a wr ite will not be executed to that byte / column location. basic write timing parameters for dq are shown in figure; they apply to all write operations. basic write timing parameters during write bursts, the first valid data-in element will be registered on the first rising edge of dqs following the write command, and the subsequent data elements will be re gistered on successive edges of dqs. the low state of dqs between the write command and the first rising edge is called the write preamble, and the low state on dqs following the last data-in element is called the write postamble. the time between the write command and the first corresponding rising edge of dqs (t dqss ) is specified with a rel- atively wide range - from 75 % to 125 % of a clock cycle. next fig. shows the two extremes of t dqss for a burst of 4. upon completion of a burst, assuming no other commands ha ve been initiated, the dq will remain high-z and any additional input data will be ignored. /clk clk tck tch tcl di n di n dqs dqs dq, dm dq, dm tdqss tdqsh tdsh tdsh twpst twpres tds tdh tw pre tds tdh tw pres twpre tdqss tdqsh twpst tdss tdss tdqsl don't care 1) di n: data in for column n 2) 3 subsequent elem ents of data in are applied in the program m ed order following di n 3) tdqss : each rising edge of dqs must fall within the +/-25 (percentage) window of the corresponding positive clock edge tdqsl case 1: tdqss = min case 2: tdqss = max
rev 1.2 / jul. 2008 39 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series write burst (min. and max. t dqss ) /clk clk write nop nop nop nop ba, col b tdqss min don't care 1) di b = data in to column b 2) 3 subsequent elements of data in are applied in the programmed order following di b 3) a non-interrupted burst of 4 is shown 4) a10 is low with the write command (auto precharge is disabled) command address dqs dq dqs dq nop dm dm tdqss max
rev 1.2 / jul. 2008 40 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series write to write data for any write burst may be concatenated with or tr uncated with a subsequent wr ite command. in either case, a continuous flow of input data, can be maintained. the new write command can be issued on any positive edge of the clock following the previous write command.the first data-in element from the new burst is applied after either the last element of a complete d burst or the last desired data element of a longer burst which is being truncated. the new write command should be issued x cycles after th e first write command, where x equals the number of desired data-in element pairs. concatenated write bursts /clk clk write nop write nop nop ba, col b tdqss min don't care 1) di b ( n ) = data in to column b (column n) 2) 3 subsequent elements of data in are applied in the programmed order following di b. 3 subsequent elements of data in are applied in the programmed order following di n. 3) non-interrupted bursts of 4 are shown. 4) each write command may be to any active bank command address dqs dq dqs dq nop dm dm ba, col n di b di n di b di n tdqss max
rev 1.2 / jul. 2008 41 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series non-concatenated write bursts random write cycles /clk clk write nop nop write nop ba, col b don't care 1) di b ( n ) = data in to column b (or colum n n). 2) 3 subsequent elements of data in are applied in the programmed order following di b . 3 subsequent elements of data in are applied in the programmed order following di n . 3) non-interrupted bursts of 4 are shown. 4) each write command may be to any active bank and may be to the same or different devices. command address dqs dq nop di b dm tdqss max di n ba, col n /clk clk write write write write nop ba, col b don't care 1) di b etc. = data in to column b, etc. ; b', etc. = the next data in following di b, etc. according to the programmed burst order 2) programmed burst length = 2, 4 or 8 in cases shown. if burst of 4 or 8, burst would be truncated. 3) each write command may be to any active bank and may be to the same or different devices. command address write ba, col n ba, col x ba, col a ba, col g dqs dm tdqss max dq di b di b' di x di x' di n di n' di a di a'
rev 1.2 / jul. 2008 42 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series write to read data for any write burst may be followed by a subsequent read command. to follow a write without truncating the write burst, twtr should be met as shown in figure. data for any write burst may be truncated by a subsequent read command as shown in figure. note that the only data-in pairs that are registered prior to the t wtr period are written to the internal array, and any subsequent data-in must be masked with dm. /clk clk write nop nop nop nop ba, col b don't care 1) di b = data in to column b . 3 subsequent elements of data in are applied in the programmed order following di b. 2) a non-interrupted burst of 4 is shown. 3) twtr is referenced from the positive clock edge after the last data in pair. 4) a10 is low with the write command (auto precharge is disabled) 5) the read and write commands are to the same device but not necessarily to the same bank. command address dqs dq read dm tdqss max ba, col n twtr cl=3 nop di b
rev 1.2 / jul. 2008 43 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series interrupting write to read /clk clk write nop nop read nop ba, col b don't care 1) di b = data in to column b. do n = data out from column n. 2) an interrupted burst of 4 is shown, 2 data elements are written. 3 subsequent elements of data in are applied in the programmed order following di b. 3) twtr is referenced from the positive clock edge after the last data in pair. 4) a10 is low with the write command (auto precharge is disabled) 5) the read and write commands are to the same device but not necessar ily to the same bank. command address dqs dq nop dm tdqss max twtr cl=3 nop di b ba, col n do n
rev 1.2 / jul. 2008 44 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series write to precharge data for any write burst may be followed by a subseque nt precharge command to the same bank (provided auto precharge was not activated). to follow a write without trun cating the write burst, twr should be met as shown in fig. non-interrupting write to precharge /clk clk write nop nop nop pre ba, col b don't care 1) di b (n) = data in to column b (column n) 3 subsequent elements of data in are applied in the programmed order following di b. 2) a non-interrupted bursts of 4 are shown. 3) twr is referenced from the positive clock edge after the last data in pair. 4) a10 is low with the write command (auto precharge is disabled) command address dqs dq nop dm tdqss max ba (a or all) twr di b
rev 1.2 / jul. 2008 45 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series data for any write burst may be truncated by a su bsequent precharge command as shown in figure. note that only data-in pairs that are registered prior to the t wr period are written to the internal array, and any subse- quent data-in should be mask ed with dm, as shown in next fig. foll owing the precharge command, a subsequent command to the same bank cannot be issued until trp is met. interrupting write to precharge /clk clk write nop nop nop nop ba, col b don't care 1) di b = data in to column b . 2) an interrupted burst of 4 or 8 is shown, 2 data elements are written. 3) twr is referenced from the positive cloc k edge after the last desired data in pair. 4) a10 is low with the write comma nd (auto precharge is disabled) 5) *1 = can be don't care for programmed burst length of 4 6) *2 = for programmed burst length of 4, dqs becomes don't care at this point command address dqs dq pre dm tdqss max twr di b 2 1 1 1 1 ba (a or all)
rev 1.2 / jul. 2008 46 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series burst terminate the burst terminate command is used to truncate read bu rsts (with auto precharge disabled). the most recently registered read command prior to the burst terminate command will be trunca ted, as shown in the operation sec- tion of this datasheet. note the burst terminate command is not bank specif ic. this command should not be used to terminate write bursts. burst terminate command don't care cs a0~a13 we cas clk clk cke ba0, ba1 ras (high)
rev 1.2 / jul. 2008 47 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. another command to the same bank (or banks) being prec harged must not be issued until the precharge time (t rp ) is completed. if one bank is to be precharged, the particular bank addres s needs to be specified. if all banks are to be precharged, a10 should be set high along with the precharge command . if a10 is high, ba0 and ba1 are ignored. a precharge command will be treated as a nop if there is no open row in that bank, or if the previously open row is already in the process of precharging. precharge command auto precharge auto precharge is a feature which performs the same individu al bank precharge function as described above, but with- out requiring an explicit command. this is accomplished by using a10 (a10=h igh), to enable auto precharge in conj unction with a specific read or write command. this precharges the bank/row afte r the read or write burst is complete. auto precharge is non persistent, so it should be enabled with a read or write command each time auto precharge is desired. auto precharge ensures that a precharge is in itiated at the earliest valid stage within a burst. the user must not issue another command to the same bank until the precharge time (t rp ) is completed. don' t care ba bank address a10 defines the precharge mode when a precharge command, a read command or a write command is issued. if a10 = high when a precharge command is issued, all banks are precharged. if a10 = low when a precharge command is issued, only the bank that is selected by ba1/ba0 is precharged. if a10 = high when read or wr i t e command, aut o- precharge function is enabled. whi l e a10 = l o w, a u t o- precharge function is disabled. cs a0~a9, a11~a13 we cas clk clk cke ba0, ba1 ras a10 (high)
rev 1.2 / jul. 2008 48 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series auto refresh and self refresh mobile ddr devices require a refresh of all rows in any rol ling 64ms interval. each refres h is generated in one of two ways: by an explicit auto refresh command, or by an internally timed event in self refresh mode: auto refresh. this command is used during normal operation of the mobile ddr. it is non persistent, so must be issued each time a refresh is required. the refresh addressing is generated by the internal refresh controller.the mobile ddr requires auto refresh commands at an average periodic interval of t refi . to allow for improved efficiency in sc heduling and switching between tasks, some flexibility in the absolute refresh interval is provided. a maximum of eight auto refresh co mmands can be posted to any given mobile ddr, and the maximum absolute interval between any auto refresh command and the next auto refresh command is 8*t refi . -self refresh. this state retains data in the mobile dd r, even if the rest of the system is powered down (even without external clock- ing). note refresh interval timing while in self refresh mo de is scheduled internally in the mobile ddr and may vary and may not meet trefi time. ''don't care'' except cke, which must remain low. an internal refresh cycle is scheduled on self refresh entry. the pro- cedure for exiting self refresh mode requires a series of commands. first clock must be stable before cke going high. nop commands should be issued for the duration of the refresh exit time (t xsr ), because time is required for the com- pletion of any internal refresh in progress. the use of self refresh mode introduces the possibility th at an internally timed event can be missed when cke is raised for exit from self refresh mode. upon exit from self refresh an extra auto refresh command is recom- mended. in the self refresh mode, two additional power-savi ng options exist. they are temperature compensated self refresh and partial array self refresh and are described in the extended mode register section. the self refresh command is used to retain cell data in th e mobile sdram. in the self refresh mode, the mobile sdram operates refresh cycle asynchronously. the self refresh command is initiated like an auto refresh command except ck e is disabled (low). the mobile ddr can accomplish an special self refresh operation by the sp ecific modes (pasr) programmed in extended mode regis- ters. the mobile ddr can control the refr esh rate automatically by the temperature value of auto tcsr (temperature compensated self refresh) to reduce self refresh current and select the memory array to be refreshed by the value of pasr (partial array self refresh). the mobile ddr can reduce the self refresh current(i dd6 ) by using these two modes.
rev 1.2 / jul. 2008 49 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series don't care auto refresh command self refresh command cs a0~a13 we cas clk clk cke ba0, ba1 ras cs a0~a13 we cas clk clk cke ba0, ba1 ras (high)
rev 1.2 / jul. 2008 50 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series self refresh entry and exit /clk clk enter self refresh mode pre nop arf nop nop nop arf nop act pre all cke command address a10(ap) dq ba a row n row n high-z exit self refresh mode any command (auto refresh recommended) cont't care trp trfc txsr trfc
rev 1.2 / jul. 2008 51 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series mode register set the mode register and the extended mode register are load ed via the address bits. ba0 and ba1 are used to select among the mode register, the extended mode register and st atus register. see the mode register description in the register definition section. the mode register set comma nd can only be issued when all banks are idle and no bursts are in progress, and a subsequent ex ecutable command cannot be issued until t mrd is met. mode register set command code = mode register / extended mode register selection (ba0, ba1) and op-code (a0 - an) tmrd definition mrs nop valid code valid tmrd /clk clk command address don't care don't care code code cs a0~a13 we cas clk clk cke ba0, ba1 ras (high)
rev 1.2 / jul. 2008 52 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series mode register the mode register contains the specific mode of operation of the mobile ddr sdram. this register includes the selec- tion of a burst length(2, 4 or 8), a cas latency(2 or 3), a burst type. the mode register set must be done before any activate command after the power up sequ ence. any contents of the mode regist er be altered by re-programming the mode register through the executio n of mode register set command. mode register set burst length read and write accesses to the mobile ddr sdram are burs t oriented, with the burst le ngth being programmable, as shown in page10. the burst length dete rmines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 2, 4 or 8 locations are available for both the sequential and the interleaved burst types. burst type accesses within a given burst may be programmed to be either sequential or interleaved. cas latency the cas latency is the delay between the registration of a re ad command and the availability of the first piece of out- put data. if a read command is registered at a clock edge n and the latency is 3 clocks, the first data element will be valid at n + 2t ck + t ac . if a read command is registered at a clock edge n and the latency is 2 clocks, the first data element will be valid at n + t ck + t ac . clk clk precharge all bank mode register set cmd tck command (any) 0 1 234 56 trp 2 clk min
rev 1.2 / jul. 2008 53 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series extended mode register the extended mode register contains the specific featur es of self refresh operation of the mobile ddr sdram. the extended mode register is programmed via the mo de register set command (with ba1=1 and ba0=0) and will retain the stored information until it is reprogrammed, the device is put in deep po wer-down mode, or the device loses power. the extended mode register should be loaded when all banks are idle and no bursts are in progress, and subsequent operation should only be initiated after t mrd . violating these requirements will result in unspecified opera- tion. the extended mode register is written by asserting low on cs , ras , cas , we and high on ba0. the state of address pins a0 ~ a13 and ba1 in the same cycle as cs , ras , cas and we going low are written in the extended mode regis- ter. the extended mode register must be loaded when all banks are idle and no bursts are in progress, and the con- troller must wait the specified time before initiating any su bsequent operation. violating either of these requirements will result in unspecified operation. this register includes the selection of partial array to be refreshed (full array, half arra y, quarter array, etc.). the extended mode register set must be done before any acti vate command after the power up sequence. any contents of the mode register be altered by re-programming the mode register through the execution of extended mode register set command. partial array self refresh (pasr) with pasr, the self refresh may be restricted to a variable portion of the total array. the whole array (default), 1/2 array, 1/4 array, 1/8 array or 1/16 array could be selected. drive strength (ds) the drive strength could be set to full or half via address bi ts a5 and a6. the half drive st rength is intended for lighter loads or point-to-p oint environments.
rev 1.2 / jul. 2008 54 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series status register read the status register contains the specific die information su ch as density, device type, data bus width, refresh rate, revision id and manufacturers. the status register is only for read. below figure is status register read timing dia- gram. to read out the status register values, ba[1:0] set to 01 b and a[13:0] set to all 0 with mrs command followed by read command with that ba[1:0] and a[13:0] are don?t care. note) 1. srr can only be issued after power-up sequence is complete. 2. srr can only be issued with all banks precharged. 3. srr cl is unchanged from value in the mode register. 4. srr bl is fixed at 2. 5. tsrr = 2 clk (min) 6. tsrc = cl + 1. (min time between read to next valid command) 7. no commands other than nop and deselect are allowed between the srr and the read. cmd tck trp tsrr nop mrs nop read nop nop nop cmd register value out tsrc clk clk cmd ba[1:0] add dqs dq[15:0] 01 0 cl = 3 don s t care pre all or pre
rev 1.2 / jul. 2008 55 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series power down power down occurs if cke is set low coincident with devi ce deselect or nop command and when no accesses are in progress. if power down occurs when all banks are idle, it is precharge power down. if power down occurs when one or more banks are active, it is referred to as active power down. the device cannot stay in this mode for longer than the refresh requirements of the device, without losing data. the power down state is exited by setting cke high while issuing a device deselect or nop command. a valid command can be issued after t xp . for clock stop during power down mode, please refer to the clock stop sub- section in operation section of this datasheet. note: this case shows cke low coincident with no operation. alternately power down entry can be ac hieved with cke low coincide nt with device deselect. deep power down the deep power down (dpd) mode enables very low standby currents. all internal voltage generators inside the mobile ddr sdram are stopped and all memory data is lost in this mode. all the information in the mode register and the extended mode register is lost. next figure, deep power down command shows the deep power down command all banks must be in idle state with no activity on the data bus prior to entering the dpd mode. while in this st ate, cke must be held in a constant low state. to exit the dpd mode, cke is taken high after the clock is stable and nop command must be maintained for at least 200 us. after 200 us a complete re-initialization routing is required following steps 4 through 11 as defined in power- up and initialization sequences. dpd is an optional feat ure, so please contact hynix office for the dpd feature. don't care don't care deep power down entry command power-down entry command cs a0~a13 we cas clk clk cke ba0, ba1 ras cs a0~a13 we cas clk clk cke ba0, ba1 ras
rev 1.2 / jul. 2008 56 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series mobile ddr sdram deep power down entry and exit before entering deep power down the dram must be in an al l banks idle state with no acti vity on the data bus. upon entering deep power down all data will be lost. while in de ep power down cke must be held in a constant low state. upon exiting deep power down nop command must be mainta ined for 200us. after 200us a complete initialization routine is required following steps 4 through 11 as defined in power-up and initialization sequences. mobile ddr sdram deep power-down entry and exit note: 1. clock must be stable before exiting deep power down mode. that is, the clock must be cycling within specifications by ta0. 2. device must be in the all banks idle state prior to entering deep power down mode. 3. 200us is required before any command can be applied upon exiting dpd. 4. dpd = deep power down command. 5. upon exiting deep power down a precha rge all command must be issued followed by two auto refresh commands and a load mode register sequence. don't care nop dpd 4 nop valid 5 valid t 0 t 1 ta0 1 ta 1 tb 1 tck tih tis tch tcl tis tih tis tih tis trp 2 deep power down mode exit deep power down mode t=200us 3 ck ck cke com add dqs dq dm tis
rev 1.2 / jul. 2008 57 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series cas latency definition cas latency definition of mobile ddr sd ram must be must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. cas latency definition: with cl = 3 the first data element is valid at (2 * t ck + t ac ) after the clock at which the read command was registered (see figure 2) cas latency definition note 1. dq transitionin g after dqs transition define t dqsq window. 2. all dq must transition by t dqsq after dqs transitions, regardless of tac. 3. tac is the dq output window relative to ck, and is the long term component of dq skew. read nop nop nop nop t 0 t 1 t 3 t 4 t 5 t 2 t 2n t 3n t 4n t 5n t 6 nop nop t 2 t 2n t 3 t 3n t 4 t 4n t 5 t 5n all dq values, collectively 2 cl = 3 tlz trpre tlz tdqsck tdqsck trpst dqs cmd ck ck tac tdqsq
rev 1.2 / jul. 2008 58 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series clock stop mode clock stop mode is a feature supported by mobile ddr sd ram devices. it reduces clock-related power consumption during idle periods of the device. conditions: the mobile ddr sdra m supports clock stop in case: ? the last access command (active, read, write, pr echarge, auto refresh or mode register set) has executed to completion, including any data-out during read bursts; the number of required clock pulses per access command depends on the device's ac timing parameters and the clock frequency; ? the related timing condition (t rcd , t wr , t rp , t rfc , t mrd ) has been met; ? cke is held high. when all conditions have been met, the device is either in ''idle'' or ''row active'' state, and clock stop mode may be entered with ck held low and ck held high. clock stop mode is exited wh en the clock is restarted. nops command have to be issued for at least one clock cycle before the next access command may be applied. additional clock pulses might be required depending on the system characteristics. figure1 illustrates the clock stop mode: ? initially the device is in clock stop mode; ? the clock is restarted with the rising edge of t0 and a nop on the command inputs; ? with t 1 a valid access command is latched; this command is followed by nop commands in order to allow for clock stop as soon as this access command has completed; ? t n is the last clock pulse required by the access command latched with t 1. ? the timing condition of this access co mmand is met with the completion of t n ; therefore tn is the last clock pulse required by this command an d the clock is then stopped. clock stop mode ck add cmd nop nop nop nop valid clock stopped exit clock stop mode valid command enter clock stop mode don't care (high-z) ck cmd t 0 t 1 t 2 t n cke dq, dqs timing condition
rev 1.2 / jul. 2008 59 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series data mask 1,2) mobile ddr sdram uses a dq write mask enable signal (dm) which masks write data. data masking is only available in the write cycle for mobile ddr sdram. data masking is available during write, but data masking during read is not available. dm command masks burst write data with reference to data st robe signal and it is not related with read data. dm com- mand can be initiated at both the rising edge and the falling edge of the dqs. dm latency for write operation is zero. for x16 data i/o, mobile ddr sdram is equipped with ldm and udm which control dq0~dq7 and dq8~dq15 respectively. note: 1) mobile sdr sdram can mask both read and write data, bu t the read mask is not supported by mobile ddr sdram. 2) differences in functions an d specifications (next table) data masking (write cycle: bl=4) item mobile ddr sdram mobile sdr sdram data mask write mask only write mask/read mask write write dm cmd ck ck d0 d1 d3 d0 d1 d3 hi- z dqs dq data masking data masking tdqss tdqsl tds tdh tdqsh hi- z
rev 1.2 / jul. 2008 60 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series power-up and initialization sequences mobile ddr sdram must be powered up and initialized in a predefined manner . operations procedures other thank those specified may result in undefined operation. if there is any interruption to the devi ce power, the initialization routine should be followed. the steps to be follo wed for device initialization are listed below. ? step1: provide power, the device core power (v dd ) and the device i/o power (v ddq ) must be brought up simulta- neously to prevent device latch-up. although not required, it is recommended that v dd and v ddq are from the same power source. also assert and hold cl ock enable (cke) to a lvcmos logic high level. ? step 2: once the system has established consistent device power and cke is driven high, it is safe to apply stable clock. ? step 3: there must be at least 200us of valid clocks be fore any command may be given to the dram. during this time nop or deselect commands must be issued on the command bus. ? step 4: issue a precharge all command. ? step 5: provide nops or deselect commands for at least t rp time. ? step 6: issue an auto refresh command followed by nops or deselect command for at least t rfc time. issue the second auto refresh command followed by nops or deselect command for at least t rfc time. note as part of the initialization sequence there must be two auto refresh commands issued. the typical flow is to issue them at step 6, but they may also be issued between steps 10 and 11. ? step 7: using the mrs command, load the base mode register. set the desired operating modes. ? step 8: provide nops or deselect commands for at least t mrd time. ? step 9: using the mrs command, program the extended mode register for the desired operating modes. note the order of the base and extended mode register programming is not important. ? step 10: provide nop or deselct commands for at least t mrd time. ? step 11: the dram has been properly init ialized and is ready for any valid command.
rev 1.2 / jul. 2008 61 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series the initialization flow sequence is below. initialization waveform sequence vdd vddq /clk clk cke cmd dm addr a10 ba0, ba1 dq, dqs t=200usec trp tmrd trfc tmrd vdd/vddq powered up clock stable auto refresh nop arf pre mrs arf act mrs code ra code code ra code ba0=l ba1=l ba ba0=l ba1=h trfc load mode register tch tcl tck all banks tis tih tis tih tis tih tis tih don't care high-z precharge all auto refresh load extended mode register
rev 1.2 / jul. 2008 62 mobile ddr sdram 1g bit (64m x 16bit) h5ms1g62mfp series package information 60 ball 0.8mm pitch 8mm fbga [8.0 x 12.0 mm 2 , t=1.0mm max] unit [mm] 0.8 bottom view 0.340 +/-0.05 0.80 typ. 0.40 0.80 typ. 1.00 max 3.20 1.60 0.450 +/- 0.05 a1 index mark 1.375 12.00 typ. 2.40 8 . 00 t yp .

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